Signal speed requirements have been increasing with every new generation of integrated circuits (ICs). In order to support the increasing signal speed requirements for the new generation of integrated circuits, input-output (IO) buffer circuits on integrated circuits need to be capable of transferring signals at even higher speeds.
One of the ways to increase the signal transmission speed is to shrink the channel length formed between a source terminal and a drain terminal of the transistor. Such shrinking may be a natural consequence of adopting a new semiconductor process node.
However, the shrinking of the channel length may increase a transistor's susceptibility to hot carrier injection (HCI) issues. The HCI may decrease reliability of an integrated circuit by affecting a particular transistor in the integrated circuit or, as seen in some instances, may destroy the particular transistor entirely. The HCI phenomenon may occur when an electron in a transistor channel gains sufficient energy (hence the term ‘hot’) to enter the dielectric of the gate of the transistor.
In general, an HCI phenomenon may be mitigated by utilizing high voltage transistors. High voltage transistors are a type of transistors that are capable of handling elevated or “overdriven” voltages at the junctions of source or drain and the channel. Therefore, high voltage transistors are generally not susceptible to HCI phenomenon. However, utilizing high voltage transistors may not be feasible at a given process node, or may require additional manufacturing process steps, resulting in an increase of the overall manufacturing cost of a product. Therefore, utilizing high voltage transistors may be undesirable.
It is within this context that the embodiments described herein arise.